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VBSL
Vector Bitwise Select.
Syntax
VBSL
{
}{.cond
}
{datatype
}, Qd
,
Qn
Qm
VBSL
{
}{.cond
}
{datatype
}, Dd
,
Dn
Dm
where:
cond
is an optional condition code.
datatype
is an optional datatype. The assembler ignores
.datatype
Qd, Qn, Qm
specifies the destination register, the first operand register, and the second operand register, for a quadword operation.
Dd, Dn, Dm
specifies the destination register, the first operand register, and the second operand register, for a doubleword operation.
Operation
VBSL
selects each bit for the destination from the first operand if the
corresponding bit of the destination is 1, or from the second operand if the corresponding
bit of the destination is 0.