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VBSL
Vector Bitwise Select.
Syntax
VBSL{conddatatypeQdQnQm
VBSL{conddatatypeDdDnDm
where:
condis an optional condition code.
datatypeis an optional datatype. The assembler ignores
datatypeQd, Qn, Qmspecifies the destination register, the first operand register, and the second operand register, for a quadword operation.
Dd, Dn, Dmspecifies the destination register, the first operand register, and the second operand register, for a doubleword operation.
Operation
VBSL selects each bit for the destination from the first operand if the
corresponding bit of the destination is 1, or from the second operand if the corresponding
bit of the destination is 0.