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ARM Compiler armasm User Guide : VMOV2


Pseudo-instruction that generates an immediate value and places it in every element of an Advanced SIMD vector, without loading a value from a literal pool.


VMOV2{cond}.datatype Qd, #constant

VMOV2{cond}.datatype Dd, #constant



must be one of:

  • I8, I16, I32, or I64.
  • S8, S16, S32, or S64.
  • U8, U16, U32, or U64.
  • F32.

is an optional condition code.

Qd or Dd
is the extension register to be loaded.
is an immediate value of the appropriate type for datatype.


VMOV2 can generate any 16-bit immediate value, and a restricted range of 32-bit and 64-bit immediate values.

VMOV2 is a pseudo-instruction that always assembles to exactly two instructions. It typically assembles to a VMOV or VMVN instruction, followed by a VBIC or VORR instruction.

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