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ARM Compiler armasm User Guide : VLDR pseudo-instruction (floating-point)

VLDR pseudo-instruction (floating-point)

The VLDR pseudo-instruction loads a constant value into a floating-point single-precision or double-precision register.


This description is for the VLDR pseudo-instruction only.


VLDR{cond}.F64 Dd,=constant

VLDR{cond}.F32 Sd,=constant


is an optional condition code.
Dd or Sd
is the extension register to be loaded.
is an immediate value of the appropriate type for the extension register width.


If an instruction (for example, VMOV) is available that can generate the constant directly into the register, the assembler uses it. Otherwise, it generates a doubleword literal pool entry containing the constant and loads the constant using a VLDR instruction.

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