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ARM Compiler armasm User Guide : Extension register bank mapping for floating-point in AArch32 state

Extension register bank mapping for floating-point in AArch32 state

The floating-point extension register bank is a collection of registers that can be accessed as either 32-bit or 64-bit registers. It is distinct from the ARM register bank.

The following figure shows the views of the extension register bank, and the overlap between the different size registers. For example, the 64-bit register D0 is an alias for two consecutive 32-bit registers S0 and S1. The 64-bit registers D16 and D17 do not have an alias.

Figure 10-1 Extension register bank for floating-point in AArch32 state


The aliased views enable half-precision, single-precision, and double-precision values to coexist in different non-overlapped registers at the same time.

You can also use the same overlapped registers to store half-precision, single-precision, and double-precision values at different times.

Do not attempt to use overlapped 32-bit and 64-bit registers at the same time because it creates meaningless results.

The mapping between the registers is as follows:

  • S<2n> maps to the least significant half of D<n>
  • S<2n+1> maps to the most significant half of D<n>

For example, you can access the least significant half of register D6 by referring to S12, and the most significant half of D6 by referring to S13.

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