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ARM Compiler armasm User Guide : Syntax differences between UAL and A64 assembly language

Syntax differences between UAL and A64 assembly language

UAL is the assembler syntax that is used by the A32 and T32 instruction sets. A64 assembly language is the assembler syntax that is used by the A64 instruction set.

UAL in ARMv8 is unchanged from ARMv7.

The general statement format and operand order of A64 assembly language is the same as UAL, but there are some differences between them. The following table describes the main differences:

Table 6-1 Syntax differences between UAL and A64 assembly language

UAL A64

You make an instruction conditional by appending a condition code suffix directly to the mnemonic, with no delimiter. For example:

BEQ label

For conditionally executed instructions, you separate the condition code suffix from the mnemonic using a . delimiter. For example:

B.EQ label

Apart from the IT instruction, there are no unconditionally executed integer instructions that use a condition code as an operand.

A64 provides several unconditionally executed instructions that use a condition code as an operand. For these instructions, you specify the condition code to test for in the final operand position. For example:

CSEL w1,w2,w3,EQ
The .W and .N instruction width specifiers control whether the assembler generates a 32-bit or 16-bit encoding for a T32 instruction.

A64 is a fixed width 32-bit instruction set so does not support .W and .N qualifiers.

The core register names are R0-R15.

Qualify register names to indicate the operand data size, either 32-bit (W0-W31) or 64-bit (X0-X31).

You can refer to registers R13, R14, and R15 as synonyms for SP, LR, and PC respectively.

In AArch64, there is no register that is named W31 or X31. Instead, you can refer to register 31 as SP, WZR, or XZR, depending on the context. You cannot refer to PC either by name or number. LR is an alias for register 30.

A32 has no equivalent of the extend operators.

You can specify an extend operator in several instructions to control how a portion of the second source register value is sign or zero extended. For example, in the following instruction, UXTB is the extend type (zero extend, byte) and #2 is an optional left shift amount:

ADD X1, X2, W3, UXTB #2
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