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ESB

Error Synchronization Barrier.

Syntax

ESB{c}{q} ; A1 general registers (A32)

ESB{c}.W ; T1 general registers (T32)

Where:

q
Is an optional instruction width specifier. See Instruction width specifiers.
c
Is an optional instruction condition code. See Condition Codes.

Architectures supported

Supported in the Arm®v8‑A and Armv8‑R architectures.

Usage

Error Synchronization Barrier.

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