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STR (immediate offset)

Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.

Syntax

STR{type}{cond} Rt, [Rn {, #offset}] ; immediate offset

STR{type}{cond} Rt, [Rn, #offset]! ; pre-indexed

STR{type}{cond} Rt, [Rn], #offset ; post-indexed

STRD{cond} Rt, Rt2, [Rn {, #offset}] ; immediate offset, doubleword

STRD{cond} Rt, Rt2, [Rn, #offset]! ; pre-indexed, doubleword

STRD{cond} Rt, Rt2, [Rn], #offset ; post-indexed, doubleword

where:

type

can be any one of:

B

Byte

H

Halfword

-

omitted, for Word.

cond

is an optional condition code.

Rt

is the general-purpose register to store.

Rn

is the general-purpose register on which the memory address is based.

offset

is an offset. If offset is omitted, the address is the contents of Rn.

Rt2

is the additional register to store for doubleword operations.

Not all options are available in every instruction set and architecture.

Offset ranges and architectures

The following table shows the ranges of offsets and availability of this instruction:

Table 13-15 Offsets and architectures, STR, word, halfword, and byte

Instruction Immediate offset Pre-indexed Post-indexed
A32, word or byte -4095 to 4095 -4095 to 4095 -4095 to 4095
A32, halfword -255 to 255 -255 to 255 -255 to 255
A32, doubleword -255 to 255 -255 to 255 -255 to 255
T32 32-bit encoding, word, halfword, or byte -255 to 4095 -255 to 255 -255 to 255
T32 32-bit encoding, doubleword -1020 to 1020 a -1020 to 1020 a -1020 to 1020 a
T32 16-bit encoding, word b 0 to 124 a Not available Not available
T32 16-bit encoding, halfword b 0 to 62 d Not available Not available
T32 16-bit encoding, byte b 0 to 31 Not available Not available
T32 16-bit encoding, word, Rn is SP c 0 to 1020 a Not available Not available

Register restrictions

Rn must be different from Rt in the pre-index and post-index forms.

Doubleword register restrictions

Rn must be different from Rt2 in the pre-index and post-index forms.

For T32 instructions, you must not specify SP or PC for either Rt or Rt2.

For A32 instructions:

  • Rt must be an even-numbered register.
  • Rt must not be LR.
  • Arm strongly recommends that you do not use R12 for Rt.
  • Rt2 must be R(t + 1).

Use of PC

In A32 instructions you can use PC for Rt in STR word instructions and PC for Rn in STR instructions with immediate offset syntax (that is the forms that do not writeback to the Rn). However, this is deprecated.

Other uses of PC are not permitted in these A32 instructions.

In T32 code, using PC in STR instructions is not permitted.

Use of SP

You can use SP for Rn.

In A32 code, you can use SP for Rt in word instructions. You can use SP for Rt in non-word instructions in A32 code but this is deprecated.

In T32 code, you can use SP for Rt in word instructions only. All other use of SP for Rt in this instruction is not permitted in T32 code.

Example

    STR     r2,[r9,#consta-struc]   ; consta-struc is an expression
                                    ; evaluating to a constant in 
                                    ; the range 0-4095.
a 

Must be divisible by 4.

b 

Rt and Rn must be in the range R0-R7.

c 

Rt must be in the range R0-R7.

d 

Must be divisible by 2.

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