Execute system coprocessor instruction.
is an optional condition code.
is the coprocessor instruction to execute.
is an operand to the instruction. For instructions that take an argument,
Rnis compulsory. For instructions that do not take an argument,
Rnis optional and if it is not specified,
Rnmust not be PC.
You can use this pseudo-instruction to execute special coprocessor instructions such as cache, branch predictor, and TLB operations. The instructions operate by writing to special write-only coprocessor registers. The instruction names are the same as the write-only coprocessor register names and are listed in the Arm® Architecture Reference Manual. For example:
ICIALLUIS; invalidates all instruction caches Inner Shareable ; to Point of Unification and also flushes branch ; target cache.
This 32-bit instruction is available in A32 and T32.
The 32-bit T32 instruction is not available in the Armv7‑M architecture.
There is no 16-bit version of this instruction in T32.