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TT, TTT, TTA, TTAT

Test Target (Alternate Domain, Unprivileged).

Syntax

TT{cond}{q} Rd, Rn ; T1 TT general registers (T32)

TTA{cond}{q} Rd, Rn ; T1 TTA general registers (T32)

TTAT{cond}{q} Rd, Rn ; T1 TTAT general registers (T32)

TTT{cond}{q} Rd, Rn ; T1 TTT general registers (T32)

Where:

cond
Is an optional instruction condition code. See Condition Codes. It specifies the condition under which the instruction is executed. If cond is omitted, it defaults to always (AL).
q
Is an optional instruction width specifier. See Instruction width specifiers.
Rd
Is the destination general-purpose register into which the status result of the target test is written.
Rn
Is the general-purpose base register.

Usage

Test Target (TT) queries the security state and access permissions of a memory location.

Test Target Unprivileged (TTT) queries the security state and access permissions of a memory location for an unprivileged access to that location.

Test Target Alternate Domain (TTA) and Test Target Alternate Domain Unprivileged (TTAT) query the security state and access permissions of a memory location for a Non-secure access to that location. These instructions are only valid when executing in Secure state, and are UNDEFINED if used from Non-secure state.

These instructions return the security state and access permissions in the destination register, the contents of which are as follows:

Bits Name Description
[7:0] MREGION The MPU region that the address maps to. This field is 0 if MRVALID is 0.
[15:8] SREGION The SAU region that the address maps to. This field is only valid if the instruction is executed from Secure state. This field is 0 if SRVALID is 0.
[16] MRVALID Set to 1 if the MREGION content is valid. Set to 0 if the MREGION content is invalid.
[17] SRVALID Set to 1 if the SREGION content is valid. Set to 0 if the SREGION content is invalid.
[18] R Read accessibility. Set to 1 if the memory location can be read according to the permissions of the selected MPU when operating in the current mode. For TTT and TTAT, this bit returns the permissions for unprivileged access, regardless of whether the current mode is privileged or unprivileged.
[19] RW Read/write accessibility. Set to 1 if the memory location can be read and written according to the permissions of the selected MPU when operating in the current mode. For TTT and TTAT, this bit returns the permissions for unprivileged access, regardless of whether the current mode is privileged or unprivileged.
[20] NSR Equal to R AND NOT S. Can be used in combination with the LSLS (immediate) instruction to check both the MPU and SAU/IDAU permissions. This bit is only valid if the instruction is executed from Secure state and the R field is valid.
[21] NSRW Equal to RW AND NOT S. Can be used in combination with the LSLS (immediate) instruction to check both the MPU and SAU/IDAU permissions. This bit is only valid if the instruction is executed from Secure state and the RW field is valid.
[22] S Security. A value of 1 indicates the memory location is Secure, and a value of 0 indicates the memory location is Non-secure. This bit is only valid if the instruction is executed from Secure state.
[23] IRVALID

IREGION valid flag. For a Secure request, indicates the validity of the IREGION field. Set to 1 if the IREGION content is valid. Set to 0 if the IREGION content is invalid.

This bit is always 0 if the IDAU cannot provide a region number, the address is exempt from security attribution, or if the requesting TT instruction is executed from the Non-secure state.

[31:24] IREGION IDAU region number. Indicates the IDAU region number containing the target address. This field is 0 if IRVALID is0.

Invalid fields are 0.

The MREGION field is invalid and 0 if any of the following conditions are true:

  • The MPU is not present or MPU_CTRL.ENABLE is 0.
  • The address did not match any enabled MPU regions.
  • The address matched multiple MPU regions.
  • TT or TTT was executed from an unprivileged mode.

The SREGION field is invalid and 0 if any of the following conditions are true:

  • SAU_CTRL.ENABLE is set to 0.
  • The address did not match any enabled SAU regions.
  • The address matched multiple SAU regions.
  • The SAU attributes were overridden by the IDAU.
  • The instruction is executed from Non-secure state, or is executed on a processor that does not implement the Arm®v8‑M Security Extensions.

The R and RW bits are invalid and 0 if any of the following conditions are true:

  • The address matched multiple MPU regions.
  • TT or TTT is executed from an unprivileged mode.
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