imm ; A1 general registers (A32)
imm ; T1 general registers (T32)
imm ; T2 general registers (T32)
The value depends on the instruction variant:
- general registers
- For A32, is a 16-bit unsigned immediate, in the range 0 to 65535.
- T1 general registers
- For T32, is an 8-bit unsigned immediate, in the range 0 to 255.
- T2 general registers
- For T32, is a 16-bit unsigned immediate, in the range 0 to 65535.
NoteThe PE ignores the value of this constant.
- Is an optional instruction condition code. See Condition Codes.
value other than
- Is an optional instruction width specifier. See Instruction width specifiers.
Permanently Undefined generates an Undefined Instruction exception.
The encodings for
UDF used in this section are defined as permanently undefined in the Arm®v8‑A architecture. However:
- With the T32 instruction set, Arm
deprecates using the
UDFinstruction in an IT block.
- In the A32 instruction set,
UDFis not conditional.