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FCVTZS (scalar, fixed-point)

Floating-point Convert to Signed fixed-point, rounding toward Zero (scalar).

Syntax

FCVTZS Wd, Hn, #fbits ; Half-precision to 32-bit

FCVTZS Xd, Hn, #fbits ; Half-precision to 64-bit

FCVTZS Wd, Sn, #fbits ; Single-precision to 32-bit

FCVTZS Xd, Sn, #fbits ; Single-precision to 64-bit

FCVTZS Wd, Dn, #fbits ; Double-precision to 32-bit

FCVTZS Xd, Dn, #fbits ; Double-precision to 64-bit

Where:

Wd
Is the 32-bit name of the general-purpose destination register.
Hn
Is the 16-bit name of the SIMD and FP source register.
fbits

Depends on the instruction variant:

32-bit
Is the number of bits after the binary point in the fixed-point destination, in the range 1 to 32.
64-bit
Is the number of bits after the binary point in the fixed-point destination, in the range 1 to 64.
Xd
Is the 64-bit name of the general-purpose destination register.
Sn
Is the 32-bit name of the SIMD and FP source register.
Dn
Is the 64-bit name of the SIMD and FP source register.

Operation

Floating-point Convert to Signed fixed-point, rounding toward Zero (scalar). This instruction converts the floating-point value in the SIMD and FP source register to a 32-bit or 64-bit fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.

Rd = signed_convertToIntegerExactTowardZero(Vn*(2^fbits)), where R is either W or X.

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