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STUR (SIMD and FP)

Store SIMD and FP register (unscaled offset).

Syntax

STUR <Bt>, [Xn|SP{, #simm}] ; 8-bit FP/SIMD registers

STUR Ht, [Xn|SP{, #simm}] ; 16-bit FP/SIMD registers

STUR St, [Xn|SP{, #simm}] ; 32-bit FP/SIMD registers

STUR Dt, [Xn|SP{, #simm}] ; 64-bit FP/SIMD registers

STUR Qt, [Xn|SP{, #simm}] ; 128-bit FP/SIMD registers

Where:

<Bt>
Is the 8-bit name of the SIMD and FP register to be transferred.
Ht
Is the 16-bit name of the SIMD and FP register to be transferred.
St
Is the 32-bit name of the SIMD and FP register to be transferred.
Dt
Is the 64-bit name of the SIMD and FP register to be transferred.
Qt
Is the 128-bit name of the SIMD and FP register to be transferred.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.
simm
Is the optional signed immediate byte offset, in the range -256 to 255, defaulting to 0.

Usage

Store SIMD and FP register (unscaled offset). This instruction stores a single SIMD and FP register to memory. The address that is used for the store is calculated from a base register value and an optional immediate offset.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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