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CASA, CASAL, CAS, CASL, CASAL, CAS, CASL

Compare and Swap word or doubleword in memory.

Syntax

CASA Ws, Wt, [Xn|SP{,#0}] ; 32-bit, acquire general registers

CASAL Ws, Wt, [Xn|SP{,#0}] ; 32-bit, acquire and release general registers

CAS Ws, Wt, [Xn|SP{,#0}] ; 32-bit, no memory ordering general registers

CASL Ws, Wt, [Xn|SP{,#0}] ; 32-bit, release general registers

CASA Xs, Xt, [Xn|SP{,#0}] ; 64-bit, acquire general registers

CASAL Xs, Xt, [Xn|SP{,#0}] ; 64-bit, acquire and release general registers

CAS Xs, Xt, [Xn|SP{,#0}] ; 64-bit, no memory ordering general registers

CASL Xs, Xt, [Xn|SP{,#0}] ; 64-bit, release general registers

Where:

Ws
Is the 32-bit name of the general-purpose register to be compared and loaded.
Wt
Is the 32-bit name of the general-purpose register to be conditionally stored.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.
Xs
Is the 64-bit name of the general-purpose register to be compared and loaded.
Xt
Is the 64-bit name of the general-purpose register to be conditionally stored.

Architectures supported

Supported in the Arm®v8.1 architecture and later.

Usage

Compare and Swap word or doubleword in memory reads a 32-bit word or 64-bit doubleword from memory, and compares it against the value held in a first register. If the comparison is equal, the value in a second register is written to memory. If the write is performed, the read and write occur atomically such that no other modification of the memory location can take place between the read and write.

  • CASA and CASAL load from memory with acquire semantics.
  • CASL and CASAL store to memory with release semantics.
  • CAS has no memory ordering requirements.

For more information about memory ordering semantics see Load-Acquire, Store-Release in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

For information about memory accesses see Load/Store addressing modes in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

The architecture permits that the data read clears any exclusive monitors associated with that location, even if the compare subsequently fails.

If the instruction generates a synchronous Data Abort, the register which is compared and loaded, that is Ws, or Xs, is restored to the value held in the register before the instruction was executed.

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