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LDADDA, LDADDAL, LDADD, LDADDL, LDADDAL, LDADD, LDADDL

Atomic add on word or doubleword in memory.

Syntax

LDADDA Ws, Wt, [Xn|SP] ; 32-bit, acquire general registers

LDADDAL Ws, Wt, [Xn|SP] ; 32-bit, acquire and release general registers

LDADD Ws, Wt, [Xn|SP] ; 32-bit, no memory ordering general registers

LDADDL Ws, Wt, [Xn|SP] ; 32-bit, release general registers

LDADDA Xs, Xt, [Xn|SP] ; 64-bit, acquire general registers

LDADDAL Xs, Xt, [Xn|SP] ; 64-bit, acquire and release general registers

LDADD Xs, Xt, [Xn|SP] ; 64-bit, no memory ordering general registers

LDADDL Xs, Xt, [Xn|SP] ; 64-bit, release general registers

Where:

Ws
Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location.
Wt
Is the 32-bit name of the general-purpose register to be loaded.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.
Xs
Is the 64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location.
Xt
Is the 64-bit name of the general-purpose register to be loaded.

Architectures supported

Supported in the Arm®v8.1 architecture and later.

Usage

Atomic add on word or doubleword in memory atomically loads a 32-bit word or 64-bit doubleword from memory, adds the value held in a register to it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register.

  • If the destination register is not one of WZR or XZR, LDADDA and LDADDAL load from memory with acquire semantics.
  • LDADDL and LDADDAL store to memory with release semantics.
  • LDADD has no memory ordering requirements.

For more information about memory ordering semantics see Load-Acquire, Store-Release in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

For information about memory accesses see Load/Store addressing modes in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

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