LDCLRAH, LDCLRALH, LDCLRH, LDCLRLH
Atomic bit clear on halfword in memory.
Xn|SP] ; Acquire general registers
Xn|SP] ; Acquire and release general registers
Xn|SP] ; No memory ordering general registers
Xn|SP] ; Release general registers
- Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location.
- Is the 32-bit name of the general-purpose register to be loaded.
- Is the 64-bit name of the general-purpose base register or stack pointer.
Supported in the Arm®v8.1 architecture and later.
Atomic bit clear on halfword in memory atomically loads a 16-bit halfword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register.
- If the destination register is not
LDCLRALHload from memory with acquire semantics.
LDCLRALHstore to memory with release semantics.
LDCLRHhas no memory ordering requirements.
For more information about memory ordering semantics see Load-Acquire, Store-Release in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.
For information about memory accesses see Load/Store addressing modes in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.