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LDR (immediate)

Load Register (immediate).

Syntax

LDR Wt, [Xn|SP], #simm ; 32-bit, Post-index

LDR Xt, [Xn|SP], #simm ; 64-bit, Post-index

LDR Wt, [Xn|SP, #simm]! ; 32-bit, Pre-index

LDR Xt, [Xn|SP, #simm]! ; 64-bit, Pre-index

LDR Wt, [Xn|SP{, #pimm}] ; 32-bit

LDR Xt, [Xn|SP{, #pimm}] ; 64-bit

Where:

Wt
Is the 32-bit name of the general-purpose register to be transferred.
simm
Is the signed immediate byte offset, in the range -256 to 255.
Xt
Is the 64-bit name of the general-purpose register to be transferred.
pimm

Depends on the instruction variant:

32-bit general registers
Is the optional positive immediate byte offset, a multiple of 4 in the range 0 to 16380, defaulting to 0.
64-bit general registers
Is the optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.

Usage

Load Register (immediate) loads a word or doubleword from memory and writes it to a register. The address that is used for the load is calculated from a base register and an immediate offset. For information about memory accesses, see Load/Store addressing modes in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile. The Unsigned offset variant scales the immediate offset value by the size of the value accessed before adding it to the base register value.

Note

For information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile, and particularly LDR (immediate).
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