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PRFM (immediate)

Prefetch Memory (immediate).

Syntax

PRFM (prfop|#imm5), [Xn|SP{, #pimm}]

Where:

prfop

Is the prefetch operation, defined as type<target><policy>.

type is one of:

PLD
Prefetch for load.
PLI
Preload instructions.
PST
Prefetch for store.

<target> is one of:

L1
Level 1 cache.
L2
Level 2 cache.
L3
Level 3 cache.

<policy> is one of:

KEEP
Retained or temporal prefetch, allocated in the cache normally.
STRM
Streaming or non-temporal prefetch, for data that is used only once.
imm5

Is the prefetch operation encoding as an immediate, in the range 0 to 31.

This syntax is only for encodings that are not accessible using prfop.

Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.
pimm
Is the optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0.

Usage

Prefetch Memory (immediate) signals the memory system that data memory accesses from a specified address are likely to occur in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as preloading the cache line containing the specified address into one or more caches.

The effect of an PRFM instruction is implementation defined. For more information, see Prefetch memory in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

For information about memory accesses, see Load/Store addressing modes in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

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