Prefetch Memory (register).
Is the prefetch operation, defined as
is one of:
- Prefetch for load.
- Preload instructions.
- Prefetch for store.
<target>is one of:
- Level 1 cache.
- Level 2 cache.
- Level 3 cache.
<policy>is one of:
- Retained or temporal prefetch, allocated in the cache normally.
- Streaming or non-temporal prefetch, for data that is used only once.
Is the prefetch operation encoding as an immediate, in the range 0 to 31.
This syntax is only for encodings that are not accessible using
- Is the 64-bit name of the general-purpose base register or stack pointer.
- When "option<0>" is set to 0, is the 32-bit name of the general-purpose index register.
- When "option<0>" is set to 1, is the 64-bit name of the general-purpose index register.
Is the index extend/shift specifier, defaulting to LSL, and which must be omitted for the LSL option when
amountis omitted, and can be one of
Is the index shift amount, optional only when
extendis not LSL. Where it is permitted to be optional, it defaults to #0. It is, and can be either
Prefetch Memory (register) signals the memory system that data memory accesses from a specified address are likely to occur in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as preloading the cache line containing the specified address into one or more caches.
The effect of an
PRFM instruction is implementation defined. For more information, see Prefetch memory in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.
For information about memory accesses, see Load/Store addressing modes in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.