Atomic bit clear on halfword in memory, without return.
Xn|SP] ; No memory ordering general registers
Xn|SP] ; Release general registers
- Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location.
- Is the 64-bit name of the general-purpose base register or stack pointer.
Supported in the Arm®v8.1 architecture and later.
Atomic bit clear on halfword in memory, without return, atomically loads a 16-bit halfword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory.
STCLRHhas no memory ordering semantics.
STCLRLHstores to memory with release semantics, as described in Load-Acquire, Store-Release in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.
For information about memory accesses see Load/Store addressing modes in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.