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STP

Store Pair of Registers.

Syntax

STP Wt1, Wt2, [Xn|SP], #imm ; 32-bit, Post-index

STP Xt1, Xt2, [Xn|SP], #imm ; 64-bit, Post-index

STP Wt1, Wt2, [Xn|SP, #imm]! ; 32-bit, Pre-index

STP Xt1, Xt2, [Xn|SP, #imm]! ; 64-bit, Pre-index

STP Wt1, Wt2, [Xn|SP{, #imm}] ; 32-bit, Signed offset

STP Xt1, Xt2, [Xn|SP{, #imm}] ; 64-bit, Signed offset

Where:

Wt1
Is the 32-bit name of the first general-purpose register to be transferred.
Wt2
Is the 32-bit name of the second general-purpose register to be transferred.
imm

Depends on the instruction variant:

32-bit general registers
Is the signed immediate byte offset, a multiple of 4 in the range -256 to 252.
64-bit general registers
Is the signed immediate byte offset, a multiple of 8 in the range -512 to 504.
Xt1
Is the 64-bit name of the first general-purpose register to be transferred.
Xt2
Is the 64-bit name of the second general-purpose register to be transferred.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.

Usage

Store Pair of Registers calculates an address from a base register value and an immediate offset, and stores two 32-bit words or two 64-bit doublewords to the calculated address, from two registers. For information about memory accesses, see Load/Store addressing modes in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

Note

For information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile, and particularly STP.
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