Dm ; A1 FP/SIMD registers (A32)
Dm ; T1 FP/SIMD registers (T32)
- Is an optional instruction width specifier. See Instruction width specifiers.
- Is the 32-bit name of the SIMD and FP destination register.
- Is the 64-bit name of the SIMD and FP source register.
Supported in the Arm®v8.3-A architecture and later.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.