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FABD (vector)

Floating-point Absolute Difference (vector).

Syntax

FABD Vd.T, Vn.T, Vm.T ; Vector half precision

FABD Vd.T, Vn.T, Vm.T ; Vector single-precision and double-precision

Where:

Vd
Is the name of the SIMD and FP destination register
T

Is an arrangement specifier:

Vector half precision
Can be one of 4H or 8H.
Vector single-precision and double-precision
Can be one of 2S, 4S or 2D.
Vn
Is the name of the first SIMD and FP source register
Vm
Is the name of the second SIMD and FP source register

Architectures supported (vector)

Supported in the Arm®v8.2 architecture and later.

Usage

Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD and FP register, from the corresponding floating-point values in the elements of the first source SIMD and FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD and FP register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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