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FCADD (vector)

Floating-point Complex Add.

Syntax

FCADD Vd.T, Vn.T, Vm.T, #rotate

Where:

Vd
Is the name of the SIMD and FP destination register.
T
Is an arrangement specifier, and can be one of 4H, 8H, 2S, 4S or 2D.
Vn
Is the name of the first SIMD and FP source register.
Vm
Is the name of the second SIMD and FP source register.
rotate
Is the rotation, and can be either 90 or 270.

Architectures supported (vector)

Supported in the Arm®v8.3-A architecture and later.

Usage

Floating-point Complex Add.

This instruction adds two source complex numbers from the Vm and the Vn vector registers and places the resulting complex number in the destination Vd vector register. The number of complex numbers that can be stored in the Vm, the Vn, and the Vd registers is calculated as the vector register size divided by the length of each complex number. These lengths are 16 for half-precision, 32 for single-precision, and 64 for double-precision. Each complex number is represented in a SIMP&FP register as a pair of elements with the imaginary part of the number being placed in the more significant element, and the real part of the number being placed in the less significant element. Both real and imaginary parts of the source and the resulting complex number are represented as floating-point values.

One of the two vector elements that are read from each of the numbers in the Vm source SIMD and FP register can be optionally negated based on the rotation value:

  • If the rotation is 90, the odd-numbered vector elements are negated.
  • If the rotation is 270, the even-numbered vector elements are negated.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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