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FMAXNMV (vector)

Floating-point Maximum Number across Vector.

Syntax

FMAXNMV Vd, Vn.T ; Half-precision

FMAXNMV Vd, Vn.T ; Single-precision and double-precision

Where:

V

Is the destination width specifier:

Single-precision and double-precision
Must be S.
Half-precision
Must be H.
T

Is an arrangement specifier:

Half-precision
Can be one of 4H or 8H.
Single-precision and double-precision
Must be 4S.
d
Is the number of the SIMD and FP destination register.
Vn
Is the name of the SIMD and FP source register.

Architectures supported (vector)

Supported in the Arm®v8.2 architecture and later.

Usage

Floating-point Maximum Number across Vector. This instruction compares all the vector elements in the source SIMD and FP register, and writes the largest of the values as a scalar to the destination SIMD and FP register. All the values in this instruction are floating-point values.

NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result of the comparison is the numerical value, otherwise the result is identical to FMAX (scalar).

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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