Floating-point Minimum Number (vector).
T ; Half-precision
T ; Single-precision and double-precision
Is an arrangement specifier:
Can be one of
- Single-precision and double-precision
Can be one of
- Is the name of the SIMD and FP destination register.
- Is the name of the first SIMD and FP source register.
- Is the name of the second SIMD and FP source register.
Architectures supported (vector)
Supported in the Arm®v8.2 architecture and later.
Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD and FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD and FP register.
NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMIN (scalar).
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.