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LD1 (vector, single structure)

Load one single-element structure to one lane of one register.

Syntax

LD1 { Vt.B }[index], [Xn|SP] ; 8-bit

LD1 { Vt.H }[index], [Xn|SP] ; 16-bit

LD1 { Vt.S }[index], [Xn|SP] ; 32-bit

LD1 { Vt.D }[index], [Xn|SP] ; 64-bit

LD1 { Vt.B }[index], [Xn|SP], #1 ; 8-bit, immediate offset, Post-index

LD1 { Vt.B }[index], [Xn|SP], Xm ; 8-bit, register offset, Post-index

LD1 { Vt.H }[index], [Xn|SP], #2 ; 16-bit, immediate offset, Post-index

LD1 { Vt.H }[index], [Xn|SP], Xm ; 16-bit, register offset, Post-index

LD1 { Vt.S }[index], [Xn|SP], #4 ; 32-bit, immediate offset, Post-index

LD1 { Vt.S }[index], [Xn|SP], Xm ; 32-bit, register offset, Post-index

LD1 { Vt.D }[index], [Xn|SP], #8 ; 64-bit, immediate offset, Post-index

LD1 { Vt.D }[index], [Xn|SP], Xm ; 64-bit, register offset, Post-index

Where:

Vt
Is the name of the first or only SIMD and FP register to be transferred.
index

The value depends on the instruction variant:

8-bit
Is the element index, in the range 0 to 15.
16-bit
Is the element index, in the range 0 to 7.
32-bit
Is the element index, in the range 0 to 3.
64-bit
Is the element index, and can be either 0 or 1.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.
Xm
Is the 64-bit name of the general-purpose post-index register, excluding XZR.

Usage

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD and FP register without affecting the other bits of the register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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