You copied the Doc URL to your clipboard.

MVN (vector)

Bitwise NOT (vector).

This instruction is an alias of NOT.

The equivalent instruction is NOT Vd.T, Vn.T.

Syntax

MVN Vd.T, Vn.T

Where:

Vd
Is the name of the SIMD and FP destination register.
T
Is an arrangement specifier, and can be either 8B or 16B.
Vn
Is the name of the SIMD and FP source register.

Usage

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD and FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD and FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Was this page helpful? Yes No