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ORR (vector, immediate)

Bitwise inclusive OR (vector, immediate).

Syntax

ORR Vd.T, #imm8{, LSL #amount}

Where:

T

Is an arrangement specifier:

16-bit
Can be one of 4H or 8H.
32-bit
Can be one of 2S or 4S.
amount

Is the shift amount:

16-bit
Can be one of 0 or 8.
32-bit
Can be one of 0, 8, 16 or 24.

Defaults to zero if LSL is omitted.

Vd
Is the name of the SIMD and FP register.
imm8
Is an 8-bit immediate.

Usage

Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD and FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD and FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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