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ST1 (vector, single structure)

Store a single-element structure from one lane of one register.

Syntax

ST1 { Vt.B }[index], [Xn|SP] ; T1 8-bit

ST1 { Vt.H }[index], [Xn|SP] ; T1 16-bit

ST1 { Vt.S }[index], [Xn|SP] ; T1 32-bit

ST1 { Vt.D }[index], [Xn|SP] ; T1 64-bit

ST1 { Vt.B }[index], [Xn|SP], #1 ; T1 8-bit, immediate offset, Post-index

ST1 { Vt.B }[index], [Xn|SP], Xm ; T1 8-bit, register offset, Post-index

ST1 { Vt.H }[index], [Xn|SP], #2 ; T1 16-bit, immediate offset, Post-index

ST1 { Vt.H }[index], [Xn|SP], Xm ; T1 16-bit, register offset, Post-index

ST1 { Vt.S }[index], [Xn|SP], #4 ; T1 32-bit, immediate offset, Post-index

ST1 { Vt.S }[index], [Xn|SP], Xm ; T1 32-bit, register offset, Post-index

ST1 { Vt.D }[index], [Xn|SP], #8 ; T1 64-bit, immediate offset, Post-index

ST1 { Vt.D }[index], [Xn|SP], Xm ; T1 64-bit, register offset, Post-index

Where:

Vt
Is the name of the first or only SIMD and FP register to be transferred.
index

The value depends on the instruction variant:

8-bit
Is the element index, in the range 0 to 15.
16-bit
Is the element index, in the range 0 to 7.
32-bit
Is the element index, in the range 0 to 3.
64-bit
Is the element index, and can be either 0 or 1.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.
Xm
Is the 64-bit name of the general-purpose post-index register, excluding XZR.

Usage

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD and FP register to memory.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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