QADD16
Signed saturating parallel halfword-wise addition.
Syntax
QADD16{condRdRnRm
where:
condis an optional condition code.
Rdis the destination register.
Rm, Rnare the ARM registers holding the operands.
Operation
This instruction performs two signed integer additions on
the corresponding halfwords of the operands and writes the results
into the corresponding halfwords of the destination. It saturates the
results to the signed range -215 ≤ x ≤
215 -1. The Q flag is not affected even
if this operation saturates.
Register restrictions
You cannot use PC for any operand.
You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.
Condition flags
This instruction does not affect the N, Z, C, V, Q, or GE flags.
Availability
The 32-bit instruction is available in A32 and T32.
For the ARMv7-M architecture, the 32-bit T32 instruction is only available in an ARMv7E-M implementation.
There is no 16-bit version of this instruction in T32.