Signed parallel byte-wise addition.
is an optional condition code.
is the destination register.
are the ARM registers holding the operands.
This instruction performs four signed integer additions on the corresponding bytes of the operands and writes the results into the corresponding bytes of the destination. The results are modulo 28. It sets the APSR GE flags.
You cannot use PC for any operand.
You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.
This instruction does not affect the N, Z, C, V, or Q flags.
It sets the GE flags in the APSR as follows:
for bits[7:0] of the result.
for bits[15:8] of the result.
for bits[23:16] of the result.
for bits[31:24] of the result.
It sets a GE flag to 1 to indicate that the corresponding result is greater than or equal to
zero. This is equivalent to an
ADDS instruction setting the N and V
condition flags to the same value, so that the GE condition passes.
You can use these flags to control a following
The 32-bit instruction is available in A32 and T32.
For the ARMv7-M architecture, the 32-bit T32 instruction is only available in an ARMv7E-M implementation.
There is no 16-bit version of this instruction in T32.