is an optional condition code.
is the ARM register holding the first operand.
is a flexible second operand.
This instruction tests the value in a register against
It updates the condition flags on the result, but does not place
the result in any register.
TST instruction performs a
bitwise AND operation on the value in
the value of
is the same as an
ANDS instruction, except
that the result is discarded.
In this T32 instruction, you cannot use SP or PC for
In this A32 instruction, use of SP or PC is deprecated.
For A32 instructions:
If you use PC (
Rn, the value used is the address of the instruction plus 8.
You cannot use PC for any operand in any data processing instruction that has a register-controlled shift.
- Updates the N and Z flags according to the result.
- Can update the C flag during the calculation of
- Does not affect the V flag.
The following form of the
TST instruction is
available in T32 code, and is a 16-bit instruction:
must both be Lo registers.
This instruction is available A32 and T32.
TST r0, #0x3F8 TSTNE r1, r5, ASR r1