Unsigned parallel subtract and add halfwords with exchange.
is an optional condition code.
is the destination register.
are the ARM registers holding the operands.
This instruction exchanges the two halfwords of the second operand, then performs a subtraction on the two top halfwords of the operands and an addition on the bottom two halfwords. It writes the results into the corresponding halfwords of the destination. The results are modulo 216. It sets the APSR GE flags.
You cannot use PC for any operand.
You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.
This instruction does not affect the N, Z, C, V, or Q flags.
It sets the GE flags in the APSR as follows:
for bits[15:0] of the result.
for bits[31:16] of the result.
It sets GE[1:0] to 1 to indicate that the addition overflowed, generating a carry. This is
equivalent to an
ADDS instruction setting the C condition flag to 1.
It sets GE[3:2] to 1 to indicate that the subtraction gave a result greater than or equal to
zero, meaning a borrow did not occur. This is equivalent to a
instruction setting the C condition flag to 1.
You can use these flags to control a following
NoteGE[1:0] are set or cleared together, and GE[3:2] are set or cleared together.
The 32-bit instruction is available in A32 and T32.
For the ARMv7-M architecture, the 32-bit T32 instruction is only available in an ARMv7E-M implementation.
There is no 16-bit version of this instruction in T32.