Instruction Synchronization Barrier.
- Specifies an optional limitation on the barrier operation. Values are:
- Full system barrier operation. Can be omitted.
- Is an optional 4-bit unsigned immediate, in the range 0 to 15, defaulting to 15.
Instruction Synchronization Barrier flushes the pipeline in the PE, so that all instructions following the
ISB are fetched from cache or memory, after the instruction has been completed. It ensures that the effects of context changing operations executed before the
ISB instruction are visible to the instructions fetched after the
ISB. Context changing operations include changing the ASID, TLB maintenance instructions, and all changes to the System registers. In addition, any branches that appear in program order after the
ISB instruction are written into the branch prediction logic with the context that is visible after the
ISB instruction. This is needed to ensure correct execution of the instruction stream. For more information, see Instruction Synchronization Barrier (ISB) in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.