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TST (shifted register)
Test (shifted register).
This instruction is an alias of ANDS
(shifted register).
The equivalent instruction is ANDS WZR,
.Wn
, Wm
{, shift
#amount
}
Syntax
TST
Wn
, Wm
{, shift
#amount
} ; 32-bit
TST
Xn
, Xm
{, shift
#amount
} ; 64-bit
Where:
Wn
- Is the 32-bit name of the first general-purpose source register.
Wm
- Is the 32-bit name of the second general-purpose source register.
amount
-
Depends on the instruction variant:
- 32-bit general registers
- Is the shift amount, in the range 0 to 31, defaulting to 0.
- 64-bit general registers
- Is the shift amount, in the range 0 to 63, defaulting to 0.
Xn
- Is the 64-bit name of the first general-purpose source register.
Xm
- Is the 64-bit name of the second general-purpose source register.
shift
-
Is the optional shift to be applied to the final source, defaulting to LSL, and can be one of
LSL
,LSR
,ASR
, orROR
.
Operation
Test (shifted register) performs a bitwise AND operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result.
, where R
n AND shift
(R
m, amount
)
is either R
W
or X
.