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FMAXNMP (scalar)

Floating-point Maximum Number of Pair of elements (scalar).

Syntax

FMAXNMP Vd, Vn.T ; Half-precision

FMAXNMP Vd, Vn.T ; Single-precision and double-precision

Where:

V

For the half-precision variant: is the destination width specifier:

Half-precision
Must be H.
Single-precision and double-precision
Can be one of S or D.
T

For the half-precision variant: is the source arrangement specifier:

Half-precision
Must be 2H.
Single-precision and double-precision
Can be one of 2S or 2D.
d
Is the number of the SIMD and FP destination register.
Vn
Is the name of the SIMD and FP source register.

Architectures supported (scalar)

Supported in ARMv8.2 and later.

Usage

Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD and FP register and writes the largest of the floating-point values as a scalar to the destination SIMD and FP register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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