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FMLS (scalar, by element)

Floating-point fused Multiply-Subtract from accumulator (by element).

Syntax

FMLS Vd, Vn, Vm.Ts[index] ; Scalar, half-precision

FMLS Vd, Vn, Vm.Ts[index] ; Scalar, single-precision and double-precision

Where:

V

Is a width specifier, H.

Is a width specifier,S, D.

d
Is the number of the SIMD and FP destination register.
n
Is the number of the first SIMD and FP source register.
Ts

Is an element size specifier, H.

Is an element size specifier,S, D.

index

Is the element index.

Is the element index,H:L, H.

Vm
Is the name of the second SIMD and FP source register in the range 0 to 31.

Architectures supported (scalar)

Supported in ARMv8.2 and later.

Usage

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD and FP register by the specified value in the second source SIMD and FP register, and subtracts the results from the vector elements of the destination SIMD and FP register. All the values in this instruction are floating-point values.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

The following table shows the valid specifier combinations:

Table 19-7 FMLS (Scalar, single-precision and double-precision) specifier combinations

V Ts index
S S 0 to 3
D D 0 or 1
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