Unsigned saturating Rounded Shift Right Narrow (immediate).
- Is the destination width specifier, and can be one of the values shown in Usage.
- Is the number of the SIMD and FP destination register.
- Is the source width specifier, and can be one of the values shown in Usage.
- Is the number of the first SIMD and FP source register.
- Is the right shift amount, in the range 1 to the destination operand width in bits, and can be one of the values shown in Usage.
Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD and FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD and FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN (scalar).
UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the
UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.
If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
The following table shows the valid specifier combinations:
Table 19-31 UQRSHRN (Scalar) specifier combinations
|B||H||1 to 8|
|H||S||1 to 16|
|S||D||1 to 32|