Floating-point Add Pairwise (vector).
T ; Half-precision
T ; Single-precision and double-precision
For the half-precision variant: is an arrangement specifier:
Can be one of
- Single-precision and double-precision
Can be one of
- Is the name of the SIMD and FP destination register.
- Is the name of the first SIMD and FP source register.
- Is the name of the second SIMD and FP source register.
Architectures supported (vector)
Supported in ARMv8.2 and later.
Floating-point Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD and FP register after the vector elements of the second source SIMD and FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD and FP register. All the values in this instruction are floating-point values.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.