Floating-point Round to Integral, using current rounding mode (vector).
T ; Half-precision
T ; Single-precision and double-precision
For the half-precision variant: is an arrangement specifier:
Can be one of
- Single-precision and double-precision
Can be one of
- Is the name of the SIMD and FP destination register.
- Is the name of the SIMD and FP source register.
Architectures supported (vector)
Supported in ARMv8.2 and later.
Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD and FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD and FP destination register.
A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.