Bitwise inclusive OR NOT (vector).
- Is the name of the SIMD and FP destination register.
Is an arrangement specifier, and can be either
- Is the name of the first SIMD and FP source register.
- Is the name of the second SIMD and FP source register.
Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD and FP registers, and writes the result to the destination SIMD and FP register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.