You copied the Doc URL to your clipboard.

VJCVT

Javascript Convert to signed fixed-point, rounding toward Zero.

Syntax

VJCVT{q}.S32.F64 Sd, Dm ; A1 FP/SIMD registers (A32)

VJCVT{q}.S32.F64 Sd, Dm ; T1 FP/SIMD registers (T32)

Where:

q
Is an optional instruction width specifier. See Instruction width specifiers.
Sd
Is the 32-bit name of the SIMD and FP destination register.
Dm
Is the 64-bit name of the SIMD and FP source register.

Architectures supported

Supported in ARMv8.3.

Usage

Javascript Convert to signed fixed-point, rounding toward Zero. This instruction converts the double-precision floating-point value in the SIMD and FP source register to a 32-bit signed integer using the Round towards Zero rounding mode, and write the result to the general-purpose destination register. If the result is too large to be accomodated as a signed 32-bit integer, then the result is the integer modulo 232, as held in a 32-bit signed integer.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

Was this page helpful? Yes No