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MRC and MRC2

Move to ARM Register from Coprocessor. Depending on the coprocessor, you might be able to specify various additional operations.

Note

MRC2 is not supported in ARMv8.

Syntax

MRC{cond} coproc, #opcode1, Rt, CRn, CRm{, #opcode2}

MRC2{cond} coproc, #opcode1, Rt, CRn, CRm{, #opcode2}

where:

cond

is an optional condition code.

In A32 code, cond is not permitted for MRC2.

coproc

is the name of the coprocessor the instruction is for. The standard name is pn, where n is an integer whose value must be:

  • In the range 0-15 in ARMv7 and earlier.
  • 14 or 15 in ARMv8.
opcode1
is a 3-bit coprocessor-specific opcode.
opcode2
is an optional 3-bit coprocessor-specific opcode.
Rt

is the ARM destination register. Rt must not be PC.

Rt can be APSR_nzcv. This means that the coprocessor executes an instruction that changes the value of the condition flags in the APSR.

CRn, CRm

are coprocessor registers.

Usage

The use of these instructions depends on the coprocessor. See the coprocessor documentation for details.

Architectures

These 32-bit instructions are available in A32 and T32.

There are no 16-bit versions of these instructions in T32.

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