STC and STC2
Transfer Data between memory and Coprocessor.
Note
STC2
is not supported in ARMv8.Syntax
{op
L
}{
}
cond
coproc
, CRd
,
[Rn
]
{op
L
}{
}
cond
{coproc
, CRd
, [Rn
,
#-
}offset
] ; offset
addressing
{op
L
}{
}
cond
{coproc
, CRd
, [Rn
,
#-
}offset
]! ; pre-index
addressing
{op
L
}{
}
cond
{coproc
, CRd
, [Rn
],
#-
}offset
; post-index
addressing
{op
L
}{
} cond
}coproc
, CRd
, [Rn
], {option
where:
op
is one of
STC
orSTC2
.cond
is an optional condition code.
In A32 code,
is not permitted forcond
STC2
.L
is an optional suffix specifying a long transfer.
coproc
is the name of the coprocessor the instruction is for. The standard name is p
n
, wheren
is an integer whose value must be:-
In the range 0-15 in ARMv7 and earlier.
-
14 in ARMv8.
-
CRd
is the coprocessor register to store.
Rn
is the register on which the memory address is based. If PC is specified, the value used is the address of the current instruction plus eight.
-
is an optional minus sign. If - is present, the offset is subtracted from
Rn
. Otherwise, the offset is added toRn
.offset
is an expression evaluating to a multiple of 4, in the range 0 to 1020.
!
is an optional suffix. If ! is present, the address including the offset is written back into
Rn
.option
-
is a coprocessor option in the range 0-255, enclosed in braces.
Usage
The use of these instructions depends on the coprocessor. See the coprocessor documentation for details.
Architectures
These 32-bit instructions are available in A32 and T32.
There are no 16-bit versions of these instructions in T32.
Register restrictions
You cannot use PC for R
in
the pre-index and post-index instructions. These are the forms that write
back to n
R
.n
You cannot use PC for R
in T32 n
STC
and STC2
instructions.
A32 STC
and STC2
instructions where R
is PC, are deprecated.n