is an optional condition code.
is the ARM register holding the first operand.
is a flexible second operand.
This instruction tests the value in a register against
It updates the condition flags on the result, but does not place
the result in any register.
TEQ instruction performs a
bitwise Exclusive OR operation on the value in
the value of
is the same as an
EORS instruction, except
that the result is discarded.
TEQ instruction to test
if two values are equal, without affecting the V or C flags (as
TEQ is also useful for testing
the sign of a value. After the comparison, the N flag is the logical Exclusive
OR of the sign bits of the two operands.
In this T32 instruction, you cannot use SP or PC for
In this A32 instruction, use of SP or PC is deprecated.
For A32 instructions:
- If you use PC (
Rn, the value used is the address of the instruction plus 8.
- You cannot use PC for any operand in any data processing instruction that has a register-controlled shift.
- Updates the N and Z flags according to the result.
- Can update the C flag during the calculation of
- Does not affect the V flag.
This instruction is available in A32 and T32.
TEQEQ r10, r9
TEQ pc, r1, ROR r0 ; PC not permitted with register ; controlled shift