STNP (SIMD and FP)
Store Pair of SIMD and FP registers, with Non-temporal hint.
Syntax
STNP
St1, St2, [Xn|SP{, #imm}] ; 32-bit
STNP
Dt1, Dt2, [Xn|SP{, #imm}] ; 64-bit
STNP
Qt1, Qt2, [Xn|SP{, #imm}] ; 128-bit FP/SIMD registers, Signed offset
Where:
St1- Is the 32-bit name of the first SIMD and FP register to be transferred.
St2- Is the 32-bit name of the second SIMD and FP register to be transferred.
imm-
Depends on the instruction variant:
- 32-bit FP/SIMD registers
- Is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0.
- 64-bit FP/SIMD registers
- Is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0.
- 128-bit FP/SIMD registers
- Is the optional signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0.
Dt1- Is the 64-bit name of the first SIMD and FP register to be transferred.
Dt2- Is the 64-bit name of the second SIMD and FP register to be transferred.
Qt1- Is the 128-bit name of the first SIMD and FP register to be transferred.
Qt2- Is the 128-bit name of the second SIMD and FP register to be transferred.
Xn|SP- Is the 64-bit name of the general-purpose base register or stack pointer.
Usage
Store Pair of SIMD and FP registers, with Non-temporal hint. This instruction stores a pair of SIMD and FP registers to memory, issuing a hint to the memory system that the access is non-temporal. The address used for the store is calculated from an address from a base register value and an immediate offset. For information about non-temporal pair instructions, see Load/Store SIMD and Floating-point Non-temporal pair in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.