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STR (immediate, SIMD and FP)

Store SIMD and FP register (immediate offset).

Syntax

STR <Bt>, [Xn|SP], #simm ; 8-bit FP/SIMD registers, Post-index

STR Ht, [Xn|SP], #simm ; 16-bit FP/SIMD registers, Post-index

STR St, [Xn|SP], #simm ; 32-bit

STR Dt, [Xn|SP], #simm ; 64-bit

STR Qt, [Xn|SP], #simm ; 128-bit FP/SIMD registers, Post-index

STR <Bt>, [Xn|SP, #simm]! ; 8-bit FP/SIMD registers, Pre-index

STR Ht, [Xn|SP, #simm]! ; 16-bit FP/SIMD registers, Pre-index

STR St, [Xn|SP, #simm]! ; 32-bit

STR Dt, [Xn|SP, #simm]! ; 64-bit

STR Qt, [Xn|SP, #simm]! ; 128-bit FP/SIMD registers, Pre-index

STR <Bt>, [Xn|SP{, #pimm}] ; 8-bit FP/SIMD registers

STR Ht, [Xn|SP{, #pimm}] ; 16-bit FP/SIMD registers

STR St, [Xn|SP{, #pimm}] ; 32-bit

STR Dt, [Xn|SP{, #pimm}] ; 64-bit

STR Qt, [Xn|SP{, #pimm}] ; 128-bit FP/SIMD registers

Where:

<Bt>
Is the 8-bit name of the SIMD and FP register to be transferred.
simm
Is the signed immediate byte offset, in the range -256 to 255.
Ht
Is the 16-bit name of the SIMD and FP register to be transferred.
St
Is the 32-bit name of the SIMD and FP register to be transferred.
Dt
Is the 64-bit name of the SIMD and FP register to be transferred.
Qt
Is the 128-bit name of the SIMD and FP register to be transferred.
pimm

Depends on the instruction variant:

8-bit FP/SIMD registers
Is the optional positive immediate byte offset, in the range 0 to 4095, defaulting to 0.
16-bit FP/SIMD registers
Is the optional positive immediate byte offset, a multiple of 2 in the range 0 to 8190, defaulting to 0.
32-bit FP/SIMD registers
Is the optional positive immediate byte offset, a multiple of 4 in the range 0 to 16380, defaulting to 0.
64-bit FP/SIMD registers
Is the optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0.
128-bit FP/SIMD registers
Is the optional positive immediate byte offset, a multiple of 16 in the range 0 to 65520, defaulting to 0.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.

Usage

Store SIMD and FP register (immediate offset). This instruction stores a single SIMD and FP register to memory. The address that is used for the store is calculated from a base register value and an immediate offset.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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