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PSB

Profiling Synchronization Barrier.

Syntax

PSB CSYNC

Architectures supported

Supported in ARMv8.2 and later.

Usage

Profiling Synchronization Barrier. This instruction is a barrier that ensures that all existing profiling data for the current PE has been formatted, and profiling buffer addresses have been translated such that all writes to the profiling buffer have been initiated. A following DSB instruction completes when the writes to the profiling buffer have completed.

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