Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector).
T ; Vector half precision
T ; Vector single-precision and double-precision
- Is the name of the SIMD and FP destination register
For the vector half precision variant: is an arrangement specifier:
- Vector half precision
Can be one of
- Vector single-precision and double-precision
Can be one of
- Is the name of the SIMD and FP source register
Architectures supported (vector)
Supported in ARMv8.2 and later.
Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD and FP destination register.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.