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FMAXV (vector)

Floating-point Maximum across Vector.


FMAXV Vd, Vn.T ; Half-precision

FMAXV Vd, Vn.T ; Single-precision and double-precision



For the single-precision and double-precision variant: is the destination width specifier:

Single-precision and double-precision
Must be S.
Must be H.

For the half-precision variant: is an arrangement specifier:

Can be one of 4H or 8H.
Single-precision and double-precision
Must be 4S.
Is the number of the SIMD and FP destination register.
Is the name of the SIMD and FP source register.

Architectures supported (vector)

Supported in ARMv8.2 and later.


Floating-point Maximum across Vector. This instruction compares all the vector elements in the source SIMD and FP register, and writes the largest of the values as a scalar to the destination SIMD and FP register. All the values in this instruction are floating-point values.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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